MIPS and QtSPIM Simulator

Computer Organization

Five basic components of a computer are input, output, memory, datapath and control with system bus that act as the communication channel. Below is the example of system bus :

• Datapath - also known as ALU that performs arithmetic operations
• Control - component of processor that sends the signals that determine the operations of the datapath, memory, input and output
• Memory - storage area where programs are kept when the programs is running
• Input - devices that writes data to memory
• Output - devices that reads data from memory and convey result of the computation

Microprocessor Operations

Most processors will repeat three basic steps to execute one machine instruction. The process is call a machine cycle. Figure below shows the example of machine cycle :

If you aren't be able to understand the above figure, let's take a look at this video :

Introduction to MIPS R2000

The MIPS R2000 ISA has fixed-width 32 bit instructions. Fixed-width instructions are common for RISC processors because they make it easy to fetch instructions without having to decode. These instructions must be stored at word-aligned addresses (i.e., addresses divisible by 4).

The MIPS ISA instructions fall into three categories: R-type, I-type, and J-type.

R-type
R-type instructions refer to register type instructions which R-type is the most complex. This is the format of the R-type instruction, when it is encoded in machine code.

B31-26	B25-21	B20-16	B15-11	B10-6	B5-0
opcode	register s	register t	register d	shift amount	function

The prototypical R-type instruction is :

add $rd, $rs, $rt

where $rd refers to some register d (d is shown as a variable, however, to use the instruction, you must put a number between 0 and 31, inclusive for d). $rs, $rt are also registers.
The semantics of the instruction are :

R[d] = R[s] + R[t]

where the addition is signed addition.

I-type

I-type is short for "immediate type". The format of an I-type instuction looks like :





B31-26
B25-21
B20-16
B15-0
  opcode  
register s
register t
              immediate              



The prototypical I-type instruction looks like :

add $rt, $rs, immed
In this case, $rt is the destination register, and $rs is the only source register.


The semantics of the addi instruction are :

R[t] = R[s] + (IR15)16 IR15-0
where IR is instruction register; where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value.



J-type


I-type is short for "immediate type". The format of an I-type instuction looks like :





B31-26
B25-21
B20-16
B15-0
  opcode  
register s
register t
              immediate              



The prototypical I-type instruction looks like :
add $rt, $rs, immed

In this case, $rt is the destination register, and $rs is the only source register.

The semantics of the addi instruction are :

R[t] = R[s] + (IR15)16 IR15-0

where IR refers to the instruction register, the register where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value.

Publish by :

NUR AKMALIZA BT ZANURY

B031310303