Saturday, December 14, 2013



System Characteristics

  • The Dependability is important especially for storage devices.
  • Performance measures
  1. Latency(response time)
  2. throughput(bandwidth)
  3. Desktops and embedded systems for response time and diversity of device
  4. Servers 


The system dependability is and to plan the time and resources needed to complete the case.

Interconnecting Component

  • Must have interconnections between CPU, memory, I/O controllers.
  • Bus: shared communication channel
         ◦Parallel set of wires for data and synchronization of data transfer
         ◦Can become a bottleneck
  • Performance limited by physical factors                                                                                             
  1. Wire length
  2.  number of connections
  • More recent alternative: high-speed serial connections with switches
          ◦Like networks

Bus Types
  • Processor-Memory buses must short, high speed and design is matched to memory organization
  • I/O buses
             ◦Longer, allowing multiple connections
             ◦Specified by standards for interoperability
             ◦Connect to processor-memory bus through a bridge

Bus Synchronization

  • A bus can be classified as synchronous or asynchronous.
    • The time for any transaction over a synchronous bus is known in advance. In accepting and/or generating information over the bus, devices take the transaction time into account.
    • Asynchronous bus, on the other hand, depends on the availability of data and the readiness of devices to initiate bus transactions.

  • In a single bus multiprocessor system, bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus.
    • The bus arbitration logic decides, using a certain priority scheme, which processor will be granted access to the bus during a certain time interval (bus master).
      • Random priority,
      • simple rotating priority; after each arbitration cycle all priority levels are reduced one place, with the lowest priority processor taking the highest priority.
      • Equal priority; when two or more requests are made, there is equal chance of any one request being processed.
      • Least Recently Used (LRU) priority; the highest priority is given to the processor that has not used the bus for the longest time.
    • The process of passing bus master ship from one processor to another is called handshaking and requires the use of two control signals: bus request and bus grant.
      • the first indicates that a given processor is requesting master ship of the bus,
      • the second indicates that bus master ship is granted.
      • a third signal, called bus busy, is usually used to indicate whether or not the bus is currently being used.

                                                                                                            Published by:
                                                                          SITI NURHASTINI BINTI ROSALI

Input Output Introduction

Input Output Devices

Input Devices
 Input devices are devices used to input data or information into a computer. For example scanner, keyboard, mouse, joystick etc.

Output Devices
 Output device is any electronic or electromechanical equipment connected to a computer and used to transfer data out of the computer. For example speaker, monitor, floppy disk, printer etc..

:65:I/O devices can be roughly categorized as storage, communications, user-interface, and other
:65:I/O devices can be characterized by behavior, partner, data storage.

I/O Bus connection
:65:I/O Bus connection is  bus that connects the CPU to main memory on the motherboard. I/O buses, which connect the CPU with the systems other components, branch off of the system bus.

Input Output Module
:65:Input output module is the part of a modular which input and output devices are connected. Such as :
  • Interface to CPU and Memory
  • Interface to one or more peripherals
Function Of Input Output Module

  1. Control and Timing - CPU ask I/O module check status attached device,then I/O module tell the status, After that if device already,CPU request for data transfer lastly I/O module gathers the data and transfers to the CPU..
  2.  CPU Communicating - Can use Command Decoding,data,status reporting and Address recognition for the devices connected to it.
  3.  Device Communication - Involves command, status information and data transfer.
  4. Data Buffering - To overcome speed mismatch.
  5. Error Detection - Allow detecting such errors, Like paper jam,bad data etc.

Published by :
Syaqira Liyana Binti Ahmad Ghazali 
( B031310568 )



We must understand how data is represented by a computer in a view of MIPS programming language.

Character Representation

A byte we have 8 bits. A character is actually represent one byte. In American Standard code for Information Interchange (ASCII), it offered 8-bit byte to represent character.

Here is a section of an assembly language program to assemble the ASCII bit patterns.

             .asciiz                              "XYZ xyz"

Here are the bit patterns that the assembler will produce in the object module:

                  58 59 5A 20 78 79 7A 00

000 0000000NUL
000 0001101SOH
000 0010202STX
000 0011303ETX
000 0100404EOT
000 0101505ENQ
000 0110606ACK
000 0111707BEL
000 1000808BS
000 1001909HT
000 1010100ALF
000 1011110BVT
000 1100120CFF
000 1101130DCR
000 1110140ESO
000 1111150FSI
001 00001610DLE
001 00011711DC1
001 00101812DC2
001 00111913DC3
001 01002014DC4
001 01012115NAK
001 01102216SYN
001 01112317ETB
001 10002418CAN
001 10012519EM
001 1010261ASUB
001 1011271BESC
001 1100281CFS
001 1101291DGS
001 1110301ERS
001 1111311FUS
111 11111277FDEL
010 00003220?
010 00013321!
010 00103422"
010 00113523#
010 01003624$
010 01013725%
010 01103826&
010 01113927'
010 10004028(
010 10014129)
010 1010422A*
010 1011432B+
010 1100442C,
010 1101452D-
010 1110462E.
010 1111472F/
011 000048300
011 000149311
011 001050322
011 001151333
011 010052344
011 010153355
011 011054366
011 011155377
011 100056388
011 100157399
011 1010583A:
011 1011593B;
011 1100603C<
011 1101613D=
011 1110623E>
011 1111633F?
100 00006440@
100 00016541A
100 00106642B
100 00116743C
100 01006844D
100 01016945E
100 01107046F
100 01117147G
100 10007248H
100 10017349I
100 1010744AJ
100 1011754BK
100 1100764CL
100 1101774DM
100 1110784EN
100 1111794FO
101 00008050P
101 00018151Q
101 00108252R
101 00118353S
101 01008454T
101 01018555U
101 01108656V
101 01118757W
101 10008858X
101 10018959Y
101 1010905AZ
101 1011915B[
101 1100925C\
101 1101935D]
101 1110945E^
101 1111955F_

110 00009660`
110 00019761a
110 00109862b
110 00119963c
110 010010064d
110 010110165e
110 011010266f
110 011110367g
110 100010468h
110 100110569i
110 10101066Aj
110 10111076Bk
110 11001086Cl
110 11011096Dm
110 11101106En
110 11111116Fo
111 000011270p
111 000111371q
111 001011472r
111 001111573s
111 010011674t
111 010111775u
111 011011876v
111 011111977w
111 100012078x
111 100112179y
111 10101227Az
111 10111237B{
111 11001247C|
111 11011257D}
111 11101267E~

Number Representation

Although computers operate on binary numbers, in MIPS number is represented in decimal system or hexadecimal system.When you need to insert number into a register, you have to remember what kind of number system that you want to write in the program. For example, to load number 16 into register $5, we have two ways to represent decimal 16 in MIPS:

1.  ori $5, $0, 16 #load number 16 into register $5
2.  ori $5, $0, 0x10 #load number 16 into register $5

                                                                                                                      Published by:
                                                                                SITI NURHASTINI BINTI ROSALI (B031310320)


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