multiplexer

                                                                           

In design of large scale of digital systems,a single line required to carry two or more different digital signals. only one signal can be placed on one line. what is required is that device will allow us to select,the signal we wish to place on this common line. The circuit is what we called as a MULTIPLEXER.

Multiplexer is known as selector because its output is one of the inputs that are selected by a control.

Multiplexers are used as one method of reducing the number of integrated circuit packages required by a particular circuit design. This in turn reduces the cost of the system.

Assume that we have four lines, C0, C1, C2 and C3, which are to be multiplexed on a single line, Output (f). The four input lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs is to appear at the output. Call these select lines A and B.

The gate implementation of a 4-line to 1-line multiplexer is shown below:



Then, this is the circuit symbol for the above multiplexer:


Truth table for Multiplexer

Select Inputs                  A                                      B		Binary	Output=input selected
0	0	0	C0
0	1	1	C1
1	0	2	C2
1	1	3	C3

If a binary 0 (A=0 and B =0) is applied to the data-select lines, the data on input C0 appear on the data output line. The table is shows of all selection input.




A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combination circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines.

n digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2ⁿ, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

Normally, the decoder is defined by the number of inputs and the number of outputs. For example, a decoder that has 3 inputs and 8 (2^3) outputs is named as 3-to-8 decoder. 


















Note on the truth table, the decoded output appears only when the encoded input is present and the enable line has a value of 1 whereas the other output line is 0.

A decoder that contains enable inputs is also known as a decoder-demultiplexer. Thus, we have a 4-to-16 decoder produced by adding a 4th input shared among both decoders, producing 16 outputs.


                                                                                           Published by:
                                                                  SITI NURHASTINI BINTI ROSALI (B031310320)

MIPS and QtSPIM Simulator

Computer Organization

Five basic components of a computer are input, output, memory, datapath and control with system bus that act as the communication channel. Below is the example of system bus :

• Datapath - also known as ALU that performs arithmetic operations
• Control - component of processor that sends the signals that determine the operations of the datapath, memory, input and output
• Memory - storage area where programs are kept when the programs is running
• Input - devices that writes data to memory
• Output - devices that reads data from memory and convey result of the computation

Microprocessor Operations

Most processors will repeat three basic steps to execute one machine instruction. The process is call a machine cycle. Figure below shows the example of machine cycle :

If you aren't be able to understand the above figure, let's take a look at this video :

Introduction to MIPS R2000

The MIPS R2000 ISA has fixed-width 32 bit instructions. Fixed-width instructions are common for RISC processors because they make it easy to fetch instructions without having to decode. These instructions must be stored at word-aligned addresses (i.e., addresses divisible by 4).

The MIPS ISA instructions fall into three categories: R-type, I-type, and J-type.

R-type
R-type instructions refer to register type instructions which R-type is the most complex. This is the format of the R-type instruction, when it is encoded in machine code.

B31-26	B25-21	B20-16	B15-11	B10-6	B5-0
opcode	register s	register t	register d	shift amount	function

The prototypical R-type instruction is :

add $rd, $rs, $rt

where $rd refers to some register d (d is shown as a variable, however, to use the instruction, you must put a number between 0 and 31, inclusive for d). $rs, $rt are also registers.
The semantics of the instruction are :

R[d] = R[s] + R[t]

where the addition is signed addition.

I-type

I-type is short for "immediate type". The format of an I-type instuction looks like :





B31-26
B25-21
B20-16
B15-0
  opcode  
register s
register t
              immediate              



The prototypical I-type instruction looks like :

add $rt, $rs, immed
In this case, $rt is the destination register, and $rs is the only source register.


The semantics of the addi instruction are :

R[t] = R[s] + (IR15)16 IR15-0
where IR is instruction register; where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value.



J-type


I-type is short for "immediate type". The format of an I-type instuction looks like :





B31-26
B25-21
B20-16
B15-0
  opcode  
register s
register t
              immediate              



The prototypical I-type instruction looks like :
add $rt, $rs, immed

In this case, $rt is the destination register, and $rs is the only source register.

The semantics of the addi instruction are :

R[t] = R[s] + (IR15)16 IR15-0

where IR refers to the instruction register, the register where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value.

Publish by :

NUR AKMALIZA BT ZANURY

B031310303

Introduction to MIPS R2000

3.2.2 DATA ALIGNMENT

Data alignment means putting the data at a memory offset equal to some multiple of the word size, which increases the system's performance due to the way the CPU handles memory.

List data sizes Apply to MIPS chips :

3.2.2.1 MIPS Data Size

Show Data Alignment in MIPS :

3.2.2.2 Data Alignment

3.2.3 REGISTERS

Register set as well as the instruction set.

3.2.3.1 MIPS register conventions

- SPIM does not implement all of co processor 0’s register, since they are not much useful in a simulator or part of the the memory system, which is not implemented.

3.2.3.2 trap register

- SPIM provide trap registes

3.2.3.3 exception code register

- The exception code bits contain a code from the table 3.1.5 describing the cause of an exception.

3.2.4 SYSTEM CALL 

Assembly programs request a service by loading the system call (syscall) instruction.

3.2.4.1 system call function

3.3.5 MIPS ASSEMBLY LANGUAGE PROGRAM FORMAT 

MIPS Program have a format that comprises of four columns 

3.2.5.1 MIPS Program Format

Column 1 : LABEL (OPTIONAL)

          A label is usd to mark a specific point in the program.

Column 2 : OPCODE (OPERATION CODE)

          Opcode is the field that denoted the basic operation and format of an instruction.

                Example opcode : add, j, mul, div, etc

Column 3 : OPERAND

          Operand may contain registers, shift amount, label to jump into and constant or address.

Column 4 : COMMENT

              Comment is anything that follow "#" on the line.

           Example : # Invoke the operating system

Published by :

Syaqira Liyana Binti Ahmad Ghazali 

( B031310568 )

MIPS INSTRUCTION FORMAT AND ADDRESSING MODE

INSTRUCTION FORMATS

Register Type (R-Type)

• This group contains all instructions that do not require an immediate value, target offset, memory address displacement, or memory address to specify an operand. This includes arithmetic and logic with all operands in registers, shift instructions, and register direct jump instructions (jalr and jr). All R-type instructions use opcode 000000. 

Immediate Type (I-Type)

• This group includes instructions with an immediate operand, branch instructions, and load and store instructions. In the MIPS architecture, all memory accesses are handled by the main processor, so coprocessor load and store instructions are included in this group. All opcodes except 000000, 00001x, and 0100xx are used for I-type instructions.

Jump Type (J-Type)

• This group consists of the two direct jump instructions (j and jal). These instructions require a memory address to specify their operand. J-type instructions use opcodes 00001x.

Published by:

Nor Aini binti Ramlan

B031310286

SEQUENTIAL LOGIC

SEQUENTIAL LOGIC

• Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs.
• Sequential circuits must have a storage element in order to remember their previous inputs.
• The storage element can be found in flip-flop where the state of this element is a function of the previous inputs to the circuit.
• in other words, sequential logic is combinational logic with memory.
• The memory is in a present state and will advance to a next state on a clock pulse at any given time as determined by conditions.

Memory Elements And Flip Flops

• The fundamental circuit is the RS (Reset-Memory) element. 
• The JK flip-flop has an RS flip-flop at its core.
• It adds circuitry that synchronizes output transitions to a clock signal.

Flip flop

Synchronous & Asynchronous Inputs

• Synchronous inputs are those whose effect on the flip-flop output is synchronized with the clock input.

• Asynchronous inputs are those that operate independently of the synchronous inputs and the input clock signal.
• These are in fact override inputs as their status overrides the statusof all synchronous inputs and also the clock input.
• They force the flip-flop output to go to a predefined state irrespective of the logic status of the synchronous inputs.
• When active, the PRESET and CLEAR inputs place the flip-flop Q output in the ‘1’ and ‘0’ state respectively.
• When it is desired that the flip-flop functions as per the status of its synchronous inputs, the asynchronous inputs are kept in their inactive state.

JK Flip Flop

• The J-K flip-flop is the most versatile of the basic flip-flop.
• It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge.

• If J and K are both low then no change occurs.
• If J and K are both high at the clock edge then the output will toggle from one state to the other. 
• It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states.

• Above is the simplified version of the versatile JK Flip-Flop. Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1.

Published by:

Nor Aini binti Ramlan

B031310286

Digital Logic

• A universal gate is a gate which can implement any Boolean function without need to use any other gate type.
• The NAND and NOR gates are universal gates. 

 

• A NAND gate represents the complement of the AND operation. Its name is an abbreviation of NOT AND.
• The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the output, denoting that a complement operation is performed on the output of the AND gate.
• Figure below illustrates the truth table and graphical symbol of NAND gate :

By this truth table, we can construct a logic gate :

 Implementing an Inverter Using only NAND Gates 

1. All NAND input pins connect to the input signal A gives an output A’. 
2. One NAND input pin is connected to the input signal A while all other input pins are connected to logic 1. The output will be A’.  

Implementing AND Using only NAND Gates 

An AND gate can be replaced by NAND gates (The AND is replaced by a NAND gate with its output complemented by a NAND gate inverter).

Implementing OR Using only NAND Gates 

An OR gate can be replaced by NAND gates (The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters).

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.

 

• A NOR gate represents the complement of the OR operation. Its name is an abbreviation of NOT OR.
• The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output, denoting that a complement operation is performed on the output of the OR gate.
• Figure below illustrates the truth table and graphical symbol of NOR gate :

Implementing an Inverter Using only NOR Gates

1. All NOR input pins connect to the input signal A gives an output A’. 
2. One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be A’.

Implementing OR Using only NOR Gates 

An OR gate can be replaced by NOR gates (The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter)

Implementing AND Using only NOR Gates 

An AND gate can be replaced by NOR gates (The AND gate is replaced by a NOR gate with all its inputs complemented by NOR gate inverters)

Thus, the NOR gate is a universal gate since it can implement the AND, OR and 

NOT functions. 

Published by :

NUR AKMALIZA BT ZANURY

B031310303