System Characteristics
- The Dependability is important especially for storage devices.
- Performance measures
- Latency(response time)
- throughput(bandwidth)
- Desktops and embedded systems for response time and diversity of device
- Servers
Dependability
The system dependability is and to plan the time and resources needed to complete the case.
Interconnecting Component
- Must have interconnections between CPU, memory, I/O controllers.
- Bus: shared communication channel
◦Parallel set of wires for data and synchronization of data transfer
◦Can become a bottleneck
- Performance limited by physical factors
- Wire length
- number of connections
- More recent alternative: high-speed serial connections with switches
◦Like networks
Bus Types
- Processor-Memory buses must short, high speed and design is matched to memory organization
- I/O buses
◦Longer, allowing multiple connections
◦Specified by standards for interoperability
◦Connect to processor-memory bus through a bridge
Bus Synchronization
- A bus can be classified as synchronous or asynchronous.
- The time for any transaction over a synchronous bus is known in advance. In accepting and/or generating information over the bus, devices take the transaction time into account.
- Asynchronous bus, on the other hand, depends on the availability of data and the readiness of devices to initiate bus transactions.
- In a single bus multiprocessor system, bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus.
- The bus arbitration logic decides, using a certain priority scheme, which processor will be granted access to the bus during a certain time interval (bus master).
- Random priority,
- simple rotating priority; after each arbitration cycle all priority levels are reduced one place, with the lowest priority processor taking the highest priority.
- Equal priority; when two or more requests are made, there is equal chance of any one request being processed.
- Least Recently Used (LRU) priority; the highest priority is given to the processor that has not used the bus for the longest time.
- The process of passing bus master ship from one processor to another is called handshaking and requires the use of two control signals: bus request and bus grant.
- the first indicates that a given processor is requesting master ship of the bus,
- the second indicates that bus master ship is granted.
- a third signal, called bus busy, is usually used to indicate whether or not the bus is currently being used.
Published by:
SITI NURHASTINI BINTI ROSALI
(B031310320)
SITI NURHASTINI BINTI ROSALI
(B031310320)